This invention relates to a semiconductor memory circuit device (hereinbelow, termed "memory"), and more particularly to a memory constructed of complementary insulated gate field effect transistors.
In the memory, one of a plurality of memory circuits (hereinbelow, termed "memory cells" or "cells") is selected on the basis of an output signal of an address decoder circuit.
Usually, the address decoder circuit includes switching elements (for example, insulated gate field effect transistors which shall hereinafter be termed "FETs") which are connected in series or in parallel and which are respectively turned "on" or "off" by address signals.
When the memory has come to have a large capacity as in recent years, address signals of an increased number of bits are required accordingly. In correspondence with the address signals, the number of the switching elements connected in series or in parallel within the address decoder circuit is increased.
In this regard, the switching elements cause stray capacitance to exist at various nodes of the circuit and have non-negligible operating resistances themselves. Therefore, the address decoder circuit including such an increased number of switching elements has its operating speed limited seriously.
The plurality of memory cells constructed as a semiconductor integrated circuit are usually arranged on a substrate such as a semiconductor substrate in the form of a matrix. Unit decoder circuits which constitute the address decoder circuit are arranged in correspondence with the memory cell rows or columns in the matrix arrangement.
In order to effectively utilize the surface of the semiconductor substrate, the unit decoder circuits need to be arranged at locations corresponding to the pitches of the memory cell rows or memory cell columns.
Nevertheless, it is difficult to arrange the unit decoder circuits including the increased number of switching elements at these pitches described above.
The increase in the number of switching elements also results in an increase in the area of element regions on the substrate.
The address decoder circuit can be constructed of complementary insulated gate field effect transistors (hereinbelow, termed "complementary FETs") in order to lower the power dissipation by reducing the operating current thereof.
However, the address decoder circuit to be constructed of complementary FETs requires a much larger number of switching elements in comparison with an address decoder circuit as is constructed of only FETs of the single channel type. It is, therefore, desirable that the operating speed, the pitch, the area, etc. as above stated be especially considered in the design of the address decoder circuit which is constructed of complementary FETs.